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High efficiency Digital Pre- Distortion (DPD) power amplifiers are strongly demanded for compact and low-cost 3.9G

base station transmitters. JRC has recently developed the high-efficiency DPD power amplifier which consists of the multistage

amplifier using internally class-E matched GaN packaged device and the proprietary DPD reducing memory effect

distortion. The driver amplifier using GaN transistor also contributes both the high efficiency and the distortion reduction

of the multi-stage amplifier because of its distortion characteristics nearly opposite to the final amplifier. A peak limiter is

applied to reduce Peak to Average Power Ratio (PAPR) with minimum degradation of Error Vector Magnitude (EVM). We

have shown that the multi-stage power amplifier achieves 42.7% overall efficiency at 28.2W average output power (7.7dB

back-off), and the DPD cancels distortion more than 30dB.

Hirohisa Hirayama
Toru Hada
Koji Fukino
Koki Shibata
Takaaki Ishikawa
Takayoshi Sasaki
Yoshio Miyazawa
Takuya Funayama
Takashi Watanabe